As the integrated circuit (IC) technology moves forward to very large-scale integration (VLSI) circuits, circuit density of the ICs increases rapidly. More and more semiconductor components/devices are included into one IC structure, and an increased number of interconnects are included into the IC structure. Accordingly, more areas are needed on a silicon wafer to provide more space for arranging interconnects.
To meet the demands of the increased number of interconnects on a silicon wafer and for miniaturization of integrated circuits, conventionally, multi-layered interconnects are often used to provide adequate interconnection capacity for all of the semiconductor devices. A semiconductor structure having the multi-layered interconnects often includes a substrate and a zeroth metal layer or metal layer 0 (M0) in the substrate. The metal layer 0 (M0) is electrically connected to source/drain regions or a gate structure region of the semiconductor device. A conventional semiconductor device also includes a dielectric layer on the substrate to provide electrical isolation between adjacent metal layers. Through-holes are formed in the dielectric layer to expose surface portions of the metal layer 0 (M0) at the bottoms of the through-holes. A first metal layer or metal layer one (M1) fills up the through-holes. The first metal layer is electrically connected to the zeroth metal layer (M0).
However, electrical properties of the semiconductor devices having conventional multi-layered interconnects still need to be improved.